1. Field of the Invention
The present invention relates to junction field effect transistors (JFETs), and more specifically, to a JFET structure with one or more P-type silicon germanium or silicon germanium carbide gates and a method of forming the structure.
2. Description of the Related Art
Junction field effect transistors (JFETs) are often incorporated into integrated circuits and, particularly, into high speed portable devices, as resistors for power switching regulation. Ideally, such a JFET will have a low ON resistance (i.e., low resistance in the ON state, low Ron) and will also only require a low pinch off voltage (i.e., a low voltage to achieve the OFF state, low Voff). Unfortunately, with current JFET structures there is a trade-off between Ron and Voff as a function of channel region doping and gate doping. Specifically, doping to achieve low Ron typically results in a high Voff and vice versa. On the one hand, the problem is accentuated in vertical JFET structures formed in deep sub-micro technologies and beyond, where a deep STI is deployed as a field for isolation. Such a vertical JFETs exhibit high Voff because the P-type top gate is relatively shallow and the trench isolation structures that isolate the P-type top gate from the source/drain regions are relatively deep, thereby making pinch off of the P-type top gate to P-type bottom gate in the N-channel region difficult without a high voltage. On the other hand, heavy and deep ion implantation on the top gate typically results in a diffused tail that extends into N-channel region to compensate the doping in the channel. Therefore, there is a need in the art for a JFET structure configured to achieve both low Voff and low Ron.